Semiconductor device and method for manufacturing the same

ABSTRACT

A semiconductor device including a substrate, an insulating layer on the substrate and including a trench, at least one via structure penetrating the substrate and protruding above a bottom surface of the trench, and a conductive structure surrounding the at least one via structure in the trench may be provided.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application is a continuation of U.S.patent application Ser. No. 15/930,935, filed on May 13, 2020, which isa continuation of U.S. application Ser. No. 16/234,815 filed on Dec. 28,2018, now granted as U.S. Pat. No. 10,699,915 on Jun. 30, 2020, which isa continuation of U.S. application Ser. No. 15/815,032, filed on Nov.16, 2017, now granted as U.S. Pat. No. 10,211,070 on Feb. 19, 2019,which claims priority under 35 U.S.C. § 119 to Korean Patent ApplicationNo. 10-2017-0055493, filed on Apr. 28, 2017, in the Korean IntellectualProperty Office, the entire contents of each of the above-referencedapplications are hereby incorporated by reference.

BACKGROUND

Embodiments of the inventive concepts relate to semiconductor devicesand/or methods for manufacturing the same and, more particularly, tosemiconductor devices including a via structure and a pad structureand/or methods for manufacturing the same.

Techniques of stacking semiconductor devices have been developed toimprove integration densities and performance of semiconductor products.For example, in a multi-chip package technique, a plurality of chips (orsemiconductor devices) may be mounted in one semiconductor package.Further, in a system-in package technique, different kinds of chips (orsemiconductor devices) may be stacked in one semiconductor package andoperate as one system. When semiconductor devices are stacked, a methodfor improving a driving speed of the stacked semiconductor devices maybe desired. A semiconductor device may be electrically connected toanother semiconductor device or a printed circuit board through aconductive via. The conductive via may improve a transmitting speed ofelectrical signals. Reliable conductive vias have been being desired assemiconductor devices have been highly integrated.

SUMMARY

Some example embodiments of the inventive concepts may providesemiconductor devices with improved reliability and/or methods formanufacturing the same.

Some example embodiments of the inventive concepts may also providemethods for manufacturing a semiconductor device, which is capable ofimproving a yield.

According to an example embodiment of the inventive concepts, asemiconductor device includes a substrate, an insulating layer on thesubstrate, the insulating layer including a trench, at least one viastructure penetrating the substrate and protruding above a bottomsurface of the trench, and a conductive structure surrounding the atleast one via structure in the trench

According to an example embodiment of the inventive concepts, asemiconductor device includes a substrate, an insulating layer on thesubstrate, the insulating layer defining a trench, the insulating layerhaving a first top surface outside the trench, a second top surface at abottom of the trench, and a third top surface connecting the first andsecond top surfaces, the trench extending from the first top surface ofthe insulating layer to a point vertically between the first top surfaceof the insulating layer and a bottom surface of the insulating layer, atleast one conductive via structure penetrating the substrate andprotruding above the bottom surface of the trench, and at least oneconductive structure surrounding the at least one conductive viastructure in the trench.

According to an example embodiment of the inventive concepts, asemiconductor device, when viewed in a plan view, includes a first metalstructure including a first metal material, a barrier metal patternsurrounding the first metal structure, and a conductive structuresurrounding the barrier metal pattern, the conductive structureincluding a second metal material, and an insulating layer surroundingthe conductive structure.

According to an example embodiment of the inventive concepts, a methodfor manufacturing a semiconductor device includes forming a viastructure penetrating through a first surface of a substrate toward asecond surface of the substrate, the second surface being opposite tothe first surface, thinning the substrate at the second surface thereofsuch that the via structure protrudes above an adjusted second surfaceof the substrate, forming an insulating layer on the adjusted secondsurface of the substrate, forming a trench in the insulating layer tosurround a protruded portion of the via structure, providing aconductive layer on the adjusted second surface of the substrate andover the trench, planarizing the conductive layer, the via structure,and the insulating layer such that top surfaces of the conductive layer,the via structure, and the insulating layer are coplanar, and theconductive layer surrounds the via structure to form a conductivestructure, and providing a semiconductor device employing the conductivestructure.

BRIEF DESCRIPTION OF THE DRAWINGS

The inventive concepts will become more apparent in view of the attacheddrawings and accompanying detailed description.

FIG. 1 is a cross-sectional view illustrating a semiconductor deviceaccording to an example embodiment of the inventive concepts.

FIG. 2A is a plan view illustrating a semiconductor device according toan example embodiment of the inventive concepts.

FIG. 2B is a cross-sectional view taken along a line IIB′-IIB″ of FIG.2A according to an example embodiment of the inventive concepts.

FIG. 2C is an enlarged view of a region IIC of FIG. 2B.

FIG. 2D is a cross-sectional view taken along the line IIB′-IIB″according to another example embodiment of the inventive concepts.

FIG. 3A is a plan view illustrating a semiconductor device according toan example embodiment of the inventive concepts.

FIG. 3B is a cross-sectional view taken along a line IIIB-IIIB′ of FIG.3A.

FIGS. 4A to 4G are cross-sectional views illustrating a method formanufacturing a semiconductor device, according to an example embodimentof the inventive concepts.

FIG. 4H is a cross-sectional view taken along the line IIB-IIB′ of FIG.2A to explain an additional planarization process according to anexample embodiment of the inventive concepts.

FIG. 5A is a cross-sectional view illustrating a semiconductor packageaccording to an example embodiment of the inventive concepts.

FIG. 5B is an enlarged view of a region VB of FIG. 5A.

DETAILED DESCRIPTION

Semiconductor devices according to some example embodiments of theinventive concepts will be described hereinafter in detail.

FIG. 1 is a cross-sectional view illustrating a semiconductor deviceaccording to an example embodiment of the inventive concepts.

Referring to FIG. 1, a semiconductor device 10 may include a substrate100, a via structure 200, and a pad structure 300. The semiconductordevice 10 may be a semiconductor chip including a memory chip, a logicchip, or a combination thereof. The substrate 100 may be a wafer-levelor chip-level substrate. For example, the substrate 100 may include asemiconductor material such as silicon, germanium, or silicon-germanium.The substrate 100 may have a first surface 100 a and a second surface100 b that are opposite to each other. The second surface 100 b of thesubstrate 100 may be substantially parallel to the first surface 100 aof the substrate 100. The first surface 100 a of the substrate 100 maybe a back surface. An insulating layer 120 may be disposed on the firstsurface 100 a of the substrate 100. The pad structure 300 may beprovided in the insulating layer 120. The second surface 100 b of thesubstrate 100 may be a front surface. A circuit layer 110 may beprovided on the second surface 100 b of the substrate 100. Connectionterminals 400 may be provided on a bottom surface of the circuit layer110. The connection terminals 400 may include solder balls, bumps,pillars, or any combination thereof. The connection terminals 400 mayinclude a conductive material. For example, the connection terminals 400may include at least one of tin (Sn), lead (Pb), silver (Ag), or anyalloy thereof.

The via structure 200 may be provided through the substrate 100, theinsulating layer 120, and the pad structure 300. The via structure 200may be electrically connected to the pad structure 300. The viastructure 200 may be electrically connected to at least one of theconnection terminals 400. In the present disclosure, it will beunderstood that when an element is referred to as being “electricallyconnected” to another element, it may be connected directly to the otherelement or one or more intervening elements may be present. Electricalsignals may be transmitted from an external system to the semiconductordevice 10 through the connection terminals 400 and the via structure 200and/or may be transmitted from the semiconductor device 10 to theexternal system through the via structure 200 and the connectionterminals 400. In the present disclosure, it will be understood thatwhen an element, device, or system is referred to as being electricallyconnected to the semiconductor device, it may be electrically connectedto at least one of transistors of the semiconductor device. Theinsulating layer 120, the via structure 200, and the pad structure 300may be exposed at a top surface of the semiconductor device 10.

FIG. 2A is a plan view illustrating a semiconductor device according toan example embodiment of the inventive concepts. FIG. 2B is across-sectional view taken along a line IIB′-IIB″ of FIG. 2A. Further,FIG. 2B corresponds to an enlarged view of a region IIB of FIG. 1. FIG.2C is an enlarged view of a region IIC of FIG. 2B. Hereinafter, thedescriptions to the same elements as in the above example embodimentswill be omitted or mentioned briefly for the purpose of ease andconvenience in explanation.

Referring to FIGS. 1, 2A, 2B, and 2C, the semiconductor device 10 mayinclude the substrate 100, the circuit layer 110, the insulating layer120, the via structure 200, and the pad structure 300. The circuit layer110 may be provided on the second surface 100 b of the substrate 100.The circuit layer 110 may include insulating patterns 111 and 112,transistors 115, and an interconnection structure 116. The transistors115 may be formed on the second surface 100 b of the substrate 100. Afirst insulating pattern 111 may be disposed on the second surface 100 bof the substrate 100 and may cover the transistors 115. Secondinsulating patterns 112 may be disposed on the first insulating pattern111. For example, the insulating patterns 111 and 112 may include atleast one of silicon oxide, silicon nitride, or silicon oxynitride. Theinterconnection structure 116 may include a contact plug 117, aninterconnection pattern 118, and an interconnection via 119. Theinterconnection structure 116 may include a conductive material (e.g.,copper or tungsten). The contact plug 117 may penetrate the firstinsulating pattern 111 so as to be connected to the transistor 115. Theinterconnection pattern 118 may be provided between the insulatingpatterns 111 and 112. The interconnection via 119 may penetrate at leastone of the second insulating patterns 112 so as to be connected to theinterconnection pattern 118. The connection terminals 400 may beprovided on the bottom surface of the circuit layer 110. At least one ofthe transistors 115 may be electrically connected to at least one of theconnection terminals 400 through the interconnection structure 116. Aprotective layer 113 may be provided on the bottom surface of thecircuit layer 110. The protective layer 113 may not cover the connectionterminals 400. The protective layer 113 may include an insulatingmaterial (e.g., a polymer).

The insulating layer 120 may be provided on the first surface 100 a ofthe substrate 100. The insulating layer 120 may have a trench 125. Thetrench 125 may extend from a top surface 120 a of the insulating layer120 toward a bottom surface of the insulating layer 120. The trench 125may have a first width at a top surface thereof, and a second width at abottom surface thereof such that the first width is greater than thesecond width. The insulating layer 120 may include an organic insulatinglayer. For example, the insulating layer 120 may include a polymer. Thepolymer may include a photosensitive polymer. The polymer may include athermosetting polymer. The polymer may include at least one ofphotosensitive polyimide (PSPI), polybenzoxazole (PBO), orbenzocyclobutene (BCB)-based polymer. The insulating layer 120 mayinclude an organic material, and thus may be relatively soft. Forexample, the insulating layer 120 may be softer than at least one of thesubstrate 100, the pad structure 300, or the via structure 200. Theinsulating layer 120 may buffer or reduce stress applied to the padstructure 300 and the via structure 200. Warpage of the substrate 100may occur in processes of manufacturing the semiconductor device 10. Athermal expansion coefficient of the insulating layer 120 may bedifferent from a thermal expansion coefficient of the substrate 100. Forexample, the thermal expansion coefficient of the insulating layer 120may be greater than the thermal expansion coefficient of the substrate100. The warpage of the substrate 100 may be reduced or prevented byadjusting a thickness of the insulating layer 120. Hereinafter, the viastructure 200 and the pad structure 300 will be described in detail.

The via structure 200 may penetrate the substrate 100, the insulatinglayer 120, and the pad structure 300. The via structure 200 may protrudefrom the first surface 100 a of the substrate 100. An upper portion of asidewall 200 c of the via structure 200 may be surrounded by the padstructure 300. A lower portion of the sidewall 200 c of the viastructure 200 may be provided in the substrate 100. The via structure200 may further penetrate the first insulating pattern 111. The viastructure 200 may be electrically connected to at least one of thetransistors 115 through the interconnection structure 116. Further, thevia structure 200 may also be electrically connected to at least one ofthe connection terminals 400 through the interconnection structure 116.

A liner layer 205 may be interposed between the via structure 200 andthe substrate 100 and between the via structure 200 and the insulatinglayer 120. The liner layer 205 may not extend between the via structure200 and the pad structure 300. For example, the liner layer 205 mayinclude an insulating material. The insulating material may include asilicon-based insulating material.

The via structure 200 may include a barrier pattern 210, a seed pattern220, and a conductive via 230. The barrier pattern 210 may be disposedon the liner layer 205. The barrier pattern 210 may be provided alongthe sidewall 200 c of the via structure 200. For example, the barrierpattern 210 may form the sidewall 200 c of the via structure 200. Thebarrier pattern 210 may include at least one of titanium (Ti), titaniumnitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The seedpattern 220 may extend along the barrier pattern 210. The seed pattern220 may include metal. The conductive via 230 may be disposed on theseed pattern 220. For example, the conductive via 230 may have a pillarshape, and the seed pattern 220 may be disposed between the barrierpattern 210 and a sidewall of the conductive via 230. The barrierpattern 210 may be disposed between the seed pattern 220 and the linerlayer 205. The conductive via 230 may include metal (e.g., copper (Cu)or tungsten (W)). The barrier pattern 210, the seed pattern 220, and theconductive via 230 may be exposed at the top surface 120 a of theinsulating layer 120.

The pad structure 300 may be disposed on the first surface 100 a of thesubstrate 100. As illustrated in FIG. 2A, the pad structure 300 maysurround the via structure 200 when viewed in a plan view. A planarshape of the pad structure 300 may not be limited to a quadrilateralshape illustrated in FIG. 2A, but may be variously modified. The viastructure 200 may penetrate the pad structure 300. The pad structure 300may cover at least a portion of the sidewall 200 c of the via structure200. The pad structure 300 may be electrically connected to the viastructure 200. The pad structure 300 may expose the via structure 200.For example, the pad structure 300 may expose a top surface 200 a of thevia structure 200. A top surface 300 a of the pad structure 300 may besubstantially coplanar with the top surface 200 a of the via structure200. For example, the top surface 300 a of the pad structure 300 may bedisposed at the same level as or substantially similar level to the topsurface 200 a of the via structure 200. In the present disclosure, theterms “the same level” and “coplanar” may take into account a tolerancerange that may occur during a process.

The pad structure 300 may be provided in the insulating layer 120. Forexample, the pad structure 300 may be provided in the trench 125 of theinsulating layer 120. For example, the pad structure 300 may be embeddedin the insulating layer 120. The top surface 300 a of the pad structure300 may be substantially coplanar with the top surface 120 a of theinsulating layer 120. For example, the top surface 300 a of the padstructure 300 may be disposed at the same level as or substantiallysimilar level to the top surface 120 a of the insulating layer 120. Abottom surface 300 b of the pad structure 300 may be provided in theinsulating layer 120. The insulating layer 120 may be in contact with asidewall 300 c of the pad structure 300 as well as the bottom surface300 b of the pad structure 300. Thus, a contact area between the padstructure 300 and the insulating layer 120 may be increased, therebyimproving adhesive strength between the pad structure 300 and theinsulating layer 120. Thus, a phenomenon that the pad structure 300 isseparated from the insulating layer 120 may be reduced or prevented,thereby improving reliability of the semiconductor device 10.

An angle θ1 between the bottom surface 300 b and the sidewall 300 c ofthe pad structure 300 may be an obtuse angle. Thus, the contact areabetween the pad structure 300 and the insulating layer 120 may befurther increased. If the angle θ1 between the bottom surface 300 b andthe sidewall 300 c of the pad structure 300 is equal to or less than 90degrees, stress may be concentrated in an edge or corner of the padstructure 300. Here, the edge or corner of the pad structure 300 refersto a region at which the bottom surface 300 b of the pad structure 300meets the sidewall 300 c of the pad structure 300. The stress mayinclude physical stress and/or stress caused by a difference betweenthermal expansion coefficients of the pad structure 300 and theinsulating layer 120. At least one of the pad structure 300 or theinsulating layer 120 may be damaged by the stress. For example, a crackmay occur in at least one of the pad structure 300 or the insulatinglayer 120. However, according to some example embodiments of theinventive concepts, the angle θ1 between the bottom surface 300 b andthe sidewall 300 c of the pad structure 300 may be greater than 90degrees. Thus, the stress may not be concentrated in the edge or cornerof the pad structure 300. Thus, reliability of the semiconductor device10 may be improved. If the angle θ1 between the bottom surface 300 b andthe sidewall 300 c of the pad structure 300 is greater than 120 degrees,it may be difficult to form the pad structure 300. According to someexample embodiments of the inventive concepts, the angle θ1 between thebottom surface 300 b and the sidewall 300 c of the pad structure 300 maybe equal to or less than 120 degrees. For example, the angle θ1 betweenthe bottom surface 300 b and the sidewall 300 c of the pad structure 300may be greater than 90 degrees and equal to or less than 120 degrees.

The pad structure 300 may include a seed pad 310 and a conductive pad320. As illustrated in FIG. 2C, the seed pad 310 may extend along abottom surface 125 b and a sidewall 125 c of the trench 125 and an upperportion of the sidewall 200 c of the via structure 200. The seed pad 310may be in contact with the via structure 200 (e.g., the barrier pattern210). The conductive pad 320 may be disposed on the seed pad 310. Theconductive pad 320 may fill the trench 125. The conductive pad 320 mayinclude metal (e.g., copper or aluminum). The topmost surface of theseed pad 310 and a top surface of the conductive pad 320 may be exposedat the top surface 120 a of the insulating layer 120.

FIG. 2D is a cross-sectional view taken along the line IIB′-IIB″ of FIG.2A according to another example embodiment of the inventive concepts.Further, FIG. 2D is an enlarged view corresponding to the region IIB ofFIG. 1. Hereinafter, the descriptions to the same elements as in theabove example embodiments will be omitted or mentioned briefly for thepurpose of ease and convenience in explanation.

Referring to FIGS. 1, 2A, and 2D, a semiconductor device 10A may includea substrate 100, a circuit layer 110, an insulating layer 120, a viastructure 200, and a pad structure 300. The substrate 100, the circuitlayer 110, the insulating layer 120, and the pad structure 300 of FIG.2D may be the same as or substantially similar to those described abovewith reference to FIG. 2B. The via structure 200 of FIG. 2D may be thesame as or substantially similar to those described with reference toFIG. 2B. For example, the via structure 200 may penetrate the substrate100, the insulating layer 120, and the pad structure 300. However, thevia structure 200 according to the present example embodiment may not beprovided in the first insulating pattern 111 of the circuit layer 110,unlike FIG. 2B.

FIG. 3A is a plan view illustrating a semiconductor device according toan example embodiment of the inventive concepts. FIG. 3B is across-sectional view taken along a line IIIB-IIIB′ of FIG. 3A. Further,FIG. 3B corresponds to an enlarged view of a region IIIB of FIG. 1.Hereinafter, the descriptions to the same elements as in the aboveexample embodiments will be omitted or mentioned briefly for the purposeof ease and convenience in explanation.

Referring to FIGS. 1, 3A, and 3B, a semiconductor device 10B may includea substrate 100, a circuit layer 110, an insulating layer 120, a viastructure 201 and 202, and a pad structure 300. The substrate 100, thecircuit layer 110, the insulating layer 120, and the pad structure 300of FIG. 3B may be the same as or substantially similar to thosedescribed with reference to FIG. 2B. The via structure 201 and 202 mayinclude a plurality of via structures 201 and 202, and the pad structure300 may include a plurality of pad structures 300 respectivelycorresponding to the via structures 201 and 202. Each of the viastructures 201 and 202 may penetrate the substrate 100, the insulatinglayer 120, each of the pad structures 300, and the first insulatingpattern 111 of the circuit layer 110. In some example embodiments, thevia structures 201 and 202 may not be provided in the first insulatingpattern 111 of the circuit layer 110, like the via structure 200 of FIG.2D.

The via structures 201 and 202 may include a first via structure 201 anda second via structure 202 which are spaced apart from each other. Thefirst via structure 201 may be the same as or substantially similar tothe via structure 200 described with reference to FIGS. 1 to 2A to 2C.The first via structure 201 may function as a connection via. Forexample, the first via structure 201 may be electrically connected to atleast one of the transistors 115 and/or at least one of the connectionterminals 400. The first via structure 201 may include a first barrierpattern 211, a first seed pattern 221, and a first conductive via 231.The second via structure 202 may include a second barrier pattern 212, asecond seed pattern 222, and a second conductive via 232. The first andsecond barrier patterns 211 and 212 may be the same as or substantiallysimilar to the barrier pattern 210 of FIGS. 1 and 2A to 2C, the firstand second seed patterns 221 and 222 may be the same as or substantiallysimilar to the seed pattern 220 of FIGS. 1 and 2A to 2C, and the firstand second conductive vias 231 and 232 may be the same as orsubstantially similar to the conductive via 230 of FIGS. 1 and 2A to 2C.However, a shape of the second via structure 202 may be different from ashape of the first via structure 201. For example, as illustrated inFIG. 3A, a planar shape of the second via structure 202 may be differentfrom a planar shape of the first via structure 201. The second viastructure 202 may function as an alignment key. Thus, an additionalalignment key may not be formed on the first surface 100 a of thesubstrate 100 or the top surface 120 a of the insulating layer 120. Asillustrated in FIG. 3B, the second via structure 202 may be insulatedfrom the transistors 115. In some example embodiments, the second viastructure 202 may be electrically connected to at least one of thetransistors 115 through the interconnection structure 116. In this case,the second via structure 202 may function as both the alignment key andthe electrical connection via.

Each of the pad structures 300 may be provided in each of trenches 125formed in the insulating layer 120. The trench 125 may have a firstwidth at a top surface thereof, and a second width at a bottom surfacethereof such that the first width is greater than the second width. Eachof the pad structures 300 may include a seed pad 310 and a conductivepad 320. One of the pad structures 300 may cover a sidewall of the firstvia structure 201 and may be electrically connected to the first viastructure 201. Another of the pad structures 300 may cover a sidewall ofthe second via structure 202 and may be electrically connected to thesecond via structure 202. The pad structures 300 may not cover a topsurface 201 a of the first via structure 201 and a top surface 202 a ofthe second via structure 202.

A method for manufacturing a semiconductor device according to someembodiments of the inventive concepts will be described hereinafter.

FIGS. 4A to 4G are cross-sectional views illustrating a method formanufacturing a semiconductor device, according to an example embodimentof the inventive concepts. Hereinafter, the descriptions to the sametechnical features as in the above example embodiments will be omittedor mentioned briefly for the purpose of ease and convenience inexplanation. Further, a single pad structure and a single connectionterminal will be described for the purpose of ease and convenience inexplanation.

Referring to FIG. 4A, a circuit layer 110 may be formed on a secondsurface 100 b of a substrate 100, and a via structure 200 may be formedin the substrate 100. In some embodiments, transistors 115 may be formedon the second surface 100 b of the substrate 100. A first insulatingpattern 111 may be formed on the second surface 100 b of the substrate100 to cover the transistors 115.

A via hole 250 may be formed in the substrate 100 and the firstinsulating pattern 111. The via hole 250 may be formed by a patterningprocess using an etching process. A liner layer 205 may be conformallyformed on a sidewall and a bottom surface of the via hole 250. Forexample, the liner layer 205 may include at least one of silicon oxide,silicon nitride, or silicon oxynitride. A via structure 200 may beformed in the via hole 250. The via structure 200 may include a barrierpattern 210, a seed pattern 220, and a conductive via 230. The viastructure 200 may be formed by a via-middle process. For example, thevia hole 250 and the via structure 200 may be formed after the formationof the transistors 115, as illustrated in FIG. 4A. In some exampleembodiments, the via structure 200 may be formed by a via-first process.For example, the via hole 250 and the via structure 200 may be formedbefore the formation of the transistors 115 and the first insulatingpattern 111. In this case, the via structure 200 may not penetrate thefirst insulating pattern 111, like the via structure 200 of FIG. 2D.

The barrier pattern 210 may be formed on the liner layer 205. Theformation of the via structure 200 may include forming the seed pattern220 on the barrier pattern 210 and performing an electroplating processusing the seed pattern 220 as an electrode. During the electroplatingprocess, the conductive via 230 may be formed by filling the via hole250 with a conductive material. In the process of forming the conductivevia 230, it may be difficult to completely fill the via hole 250 withthe conductive material. Thus, a defect 295 (e.g., a void) may be formedin an end portion 290 of the conductive via 230. Here, the end portion290 of the conductive via 230 may be toward a first surface 100 a of thesubstrate 100. For example, the end portion 290 of the conductive via230 may be adjacent to the bottom surface of the via hole 250. A gassuch as air may occupy the defect 295. In some example embodiments, aresidue of a chemical material used in a manufacturing process mayremain in the defect 295.

Second insulating patterns 112 may be formed on the first insulatingpattern 111, and an interconnection structure 116 may be formed in thefirst and second insulating patterns 111 and 112. Thus, the circuitlayer 110 may be formed. A connection terminal 400 and a protectivelayer 113 may be formed on a bottom surface of the circuit layer 110.

Referring to FIG. 4B, a thinning process may be performed on the firstsurface 100 a of the substrate 100. The thinning process may beperformed by an etch-back process using an etchant or slurry. Thethinning process may be selectively performed on the substrate 100. Theliner layer 205 and the via structure 200 may not be removed in thethinning process. The end portion 290 of the via structure 200 mayprotrude from the first surface 100 a of the thinned substrate 100.

Referring to FIG. 4C, an insulating layer 120 may be formed on the firstsurface 100 a of the thinned substrate 100. The insulating layer 120 maybe formed by coating the first surface 100 a of the thinned substrate100 with, for example, a photosensitive polymer. The insulating layer120 may include the material described with reference to FIGS. 2A to 2C.

Referring to FIG. 4D, the insulating layer 120 may be patterned to forma preliminary trench 126. The preliminary trench 126 may be formed by aphotolithography process using a mask pattern (not shown). The viastructure 200 may be exposed by the preliminary trench 126. The endportion 290 of the via structure 200 may protrude from the preliminarytrench 126. An angle θ2 between a bottom surface 126 b and a sidewall126 c of the preliminary trench 126 may be about 90 degrees.

Referring to FIG. 4E, the insulating layer 120 may be hardened. In theprocess of hardening the insulating layer 120, a trench 125 may beformed in the insulating layer 120 such that a first width at a topsurface of the trench 125 is greater than a second width at a bottomsurface of the trench 125. The trench 125 may extend from a top surface120 a of the insulating layer 120 toward a bottom surface of theinsulating layer 120. The insulating layer 120 may be hardened by a heathardening process. The heat hardening process may be performed at atemperature higher than a room temperature (e.g., 25 degrees Celsius).The trench 125 may be formed by thermal flow of the preliminary trench126. For example, a portion of the insulating layer 120 may flow down byheat in the hardening process, and thus the trench 125 may be formed. Anangle θ1′ between a bottom surface 125 b and a sidewall 125 c of thetrench 125 may be different from the angle θ2 between the bottom surface126 b and the sidewall 126 c of the preliminary trench 126. In someexample embodiments, the angle θ1′ between the bottom surface 125 b andthe sidewall 125 c of the trench 125 may be greater than the angle θ2between the bottom surface 126 b and the sidewall 126 c of thepreliminary trench 126 of FIG. 4D. The angle θ1′ between the bottomsurface 125 b and the sidewall 125 c of the trench 125 may be greaterthan 90 degrees and equal to or less than 120 degrees. The angle θ1′between the bottom surface 125 b and the sidewall 125 c of the trench125 may be substantially equal to the angle θ1 between the bottomsurface 300 b and the sidewall 300 c of the pad structure 300illustrated in FIG. 2C. The via structure 200 may protrude from thebottom surface 125 b of the trench 125. A top surface 200 a of the viastructure 200 may be disposed at a higher level than the bottom surface125 b of the trench 125.

Referring to FIG. 4F, a portion of the liner layer 205 may be removed toexpose an upper portion of a sidewall 200 c of the via structure 200 andthe top surface 200 a of the via structure 200. For example, the endportion 290 of the via structure 200 may be exposed. The portion of theliner layer 205 may be removed by an etch-back process. The viastructure 200 and the insulating layer 120 may have an etch selectivitywith respect to the liner layer 205. The liner layer 205 disposed in thetrench 125 may be removed. After the removal of the portion of the linerlayer 205, the liner layer 205 may remain between the via structure 200and the insulating layer 120 disposed under the trench 125 and betweenthe via structure 200 and the substrate 100.

Referring to FIG. 4G, a seed layer 311 and a conductive layer 312 may besequentially formed on the first surface 100 a of the substrate 100. Theseed layer 311 may be formed by a deposition process. The seed layer 311may extend along the top surface 120 a of the insulating layer 120, thebottom surface 125 b and the sidewall 125 c of the trench 125, the upperportion of the sidewall 200 c of the via structure 200, and the topsurface 200 a of the via structure 200. The seed layer 311 may be incontact with the barrier pattern 210. The conductive layer 312 may beformed on the seed layer 311. The conductive layer 312 may be formed byan electroplating process using the seed layer 311 as an electrode. Theconductive layer 312 may fill the trench 125.

Referring again to FIG. 4G, the seed layer 311 and the conductive layer312 may be planarized to form a seed pad 310 and a conductive pad 320.The seed pad 310 and the conductive pad 320 may be formed in the trench125. Thus, a pad structure 300 including the seed pad 310 and theconductive pad 320 may be provided. The planarization process may beperformed using a chemical mechanical polishing (CMP) process. The seedlayer 311 and the conductive layer 312 disposed on the top surface 120 aof the insulating layer 120 may be removed by the planarization process.The insulating layer 120 may be planarized together with the seed layer311 and the conductive layer 312. The top surface 120 a of theinsulating layer 120 may be exposed. The pad structure 300 may beconfined in the trench 125. A top surface 300 a of the pad structure 300may be substantially coplanar with the top surface 120 a of theinsulating layer 120.

The via structure 200 may be planarized together with the seed layer 311and the conductive layer 312, and thus a portion of the via structure200 may be removed. For example, the end portion 290 of the viastructure 200 may be removed. At this time, the defect 295 may beremoved together with the end portion 290 of the via structure 200.Thus, electrical characteristics and reliability of the via structure200 may be improved. After the planarization process, the via structure200 may be exposed by the pad structure 300. The top surface 200 a ofthe planarized via structure 200 may be substantially coplanar with thetop surface 300 a of the pad structure 300 and the top surface 120 a ofthe insulating layer 120. Thus, the semiconductor device 10 of FIG. 2Bmay be manufactured.

FIG. 4H is a cross-sectional view taken along the line IIB-IIB′ of FIG.2A to explain an additional planarization process according to anexample embodiment of the inventive concepts. Hereinafter, thedescriptions to the same elements as in the above embodiments will beomitted or mentioned briefly for the purpose of ease and convenience inexplanation.

Referring to FIGS. 4G and 4H, the substrate 100 including the circuitlayer 110, the via structure 200, the insulating layer 120, the seedlayer 311, and the conductive layer 312 may be prepared. The seed layer311 and the conductive layer 312 may be formed as illustrated in FIG.4G. The conductive layer 312, the seed layer 311, and the insulatinglayer 120 may be planarized to form the pad structure 300 as illustratedin FIG. 4H. A portion of the via structure 200 may be removed by theplanarization process. After the planarization process, the defect 295of the end portion 290 of the via structure 200 may remain to form aresidual defect 296 as illustrated in FIG. 4H. The residual defect 296may be a recessed portion of the top surface 200 a of the planarized viastructure 200. The residual defect 296 may be inspected. For example,the inspection of the residual defect may be performed by measuring aflatness of the top surface 200 a of the via structure 200. The residualdefect 296 may be easily inspected because the top surface 200 a of thevia structure 200 is exposed. When the residual defect 296 is detected,an additional planarization process may be performed.

Referring to FIGS. 4H and 2B, the residual defect 296 may be removedfrom the top surface 200 a of the via structure 200 by the additionalplanarization process. The inspection of the residual defect 296 and theadditional planarization process may be repeated. The additionalplanarization process may be performed until the residual defect 296 isnot detected, and thus the top surface 200 a of the via structure 200 issubstantially flat. Thus, the electrical characteristics and reliabilityof the via structure 200 may be improved. Here, the terms ‘substantiallyflat top surface’ may take into account a tolerance range that may occurin the planarization process.

FIG. 5A is a cross-sectional view illustrating a semiconductor packageaccording to an example embodiment of the inventive concepts. FIG. 5B isan enlarged view of a region VB of FIG. 5A. Hereinafter, thedescriptions to the same elements as in the above embodiments will beomitted or mentioned briefly for the purpose of ease and convenience inexplanation.

Referring to FIGS. 5A and 5B, a semiconductor package 1 may include apackage substrate 1000, first to fourth semiconductor devices 11, 12,13, and 14, and a molding layer 5000. The package substrate 1000 mayinclude a printed circuit board (PCB) or a redistribution layer.External terminals 1001 may be disposed on a bottom surface of thepackage substrate 1000. Each of the first to third semiconductor devices11, 12, and 13 may be the same as the semiconductor device 10 of FIGS.2A to 2C, the semiconductor device 10A of FIG. 2D, or the semiconductordevice 10B of FIGS. 3A and 3B. The first, second and third semiconductordevices 11, 12 and 13 may include first, second, and third substrates1100, 2100, and 3100, first, second, and third circuit layers 1110,2110, and 3110, first, second, and third insulating layers 1120, 2120,and 3120, first, second, and third via structures 1200, 2200, and 3200,and first, second, and third pad structures 1300, 2300, and 3300,respectively. The fourth semiconductor device 14 may be the uppermostsemiconductor device. The fourth semiconductor device 14 may include afourth substrate 4100 and a fourth circuit layer 4110, but may notinclude a via structure and a pad structure. However, exampleembodiments of the inventive concepts are not limited to the number ofthe semiconductor devices 11 to 14 included in the semiconductor package1.

The first semiconductor device 11 may be mounted on the packagesubstrate 1000. The first semiconductor device 11 may be electricallyconnected to the package substrate 1000 through first connectionterminals 1400. The first semiconductor device 11 may be electricallyconnected to the external terminals 1001 through the package substrate1000. A first adhesive film 1500 may be disposed between the firstsemiconductor device 11 and the package substrate 1000 to seal or coverthe first connection terminals 1400. The first adhesive film 1500 mayinclude an insulating material. The second semiconductor device 12 maybe mounted on the first semiconductor device 11. Second connectionterminals 2400 may be provided between the first semiconductor device 11and the second semiconductor device 12.

The second connection terminals 2400 may be the connection terminals 400described with reference to FIGS. 2A and 2B, FIG. 2D, FIGS. 3A and 3B,or FIG. 4B. For example, the second connection terminals 2400 may bedisposed on a bottom surface of the second circuit layer 2110. Thesecond connection terminals 2400 may include at least one of tin, lead,silver, or any alloy thereof. The second semiconductor device 12 may bedisposed on the first semiconductor device 11 in such a way that thesecond connection terminals 2400 face the first semiconductor device 11.In some example embodiments, the first via structures 1200 may include afirst via structure 1201 and a second via structure 1202. The first viastructure 1201 and the second via structure 1202 may be the same as thefirst via structure 201 and the second via structure 202 described withreference to FIGS. 3A and 3B, respectively. For example, the second viastructure 1202 may function as an alignment key. The secondsemiconductor device 12 may be aligned with the first semiconductordevice 11 by using the second via structure 1202. In this case, anadditional alignment key may not be formed on the first substrate 1100.In some example embodiments, an alignment key (not shown) may beseparately provided on the first insulating layer 1120 or the firstsubstrate 1100. In this case, the second semiconductor device 12 may bealigned with the first semiconductor device 11 by using the alignmentkey (not shown). In this case, the second via structure 1202 may beomitted. Hereinafter, electrical connection between the first and secondsemiconductor devices 11 and 12 will be described in more detail withreference to FIG. 5B.

The second connection terminal 2400 may be electrically connected to atleast one of second transistors 2115 or the second via structure 2200 ofthe second semiconductor device 12 through a second interconnectionstructure 2116 of the second circuit layer 2110. The first pad structure1300 and the first via structure 1200 may be exposed at a top surface ofthe first semiconductor device 11. The second connection terminal 2400may be in direct contact with the first via structure 1200 and the firstpad structure 1300 through a reflow process. The second connectionterminal 2400 may be electrically connected to at least one of firsttransistors 1115 of the first semiconductor device 11 through the firstvia structure 1200, the first pad structure 1300, and a firstinterconnection structure 1116 of the first circuit layer 1110. Thesecond connection terminal 2400 may be electrically connected to thepackage substrate 1000 through the first via structure 1200. Thus, thesecond semiconductor device 12 may be electrically connected to thefirst semiconductor device 11 and the package substrate 1000.

A second adhesive film 2500 may be disposed between the firstsemiconductor device 11 and the second semiconductor device 12. Thesecond adhesive film 2500 may surround the second connection terminal2400. The second adhesive film 2500 may include an insulating material.For example, the second adhesive film 2500 may include at least one ofan epoxy-based polymer, polyimide, polyester, an acrylic polymer, orpolysulfone. The second adhesive film 2500 may not include conductiveparticles. If the top surface of the first semiconductor device 11 isnot substantially flat, it may be difficult to seal the secondconnection terminal 2400 by the second adhesive film 2500. For example,a cavity (not shown) may be formed between the first semiconductordevice 11 and the second semiconductor device 12. A defect may occur inthe semiconductor package 1 by the cavity. However, according to someexample embodiments of the inventive concepts, the top surface of thefirst semiconductor device 11 may be substantially flat. For example, atop surface 1200 a of the first via structure 1200 may be disposed atthe same level as or substantially similar level to a top surface 1300 aof the first pad structure 1300 and a top surface 1120 a of the firstinsulating layer 1120. Thus, the second adhesive film 2500 may seal thesecond connection terminal 2400 well. Accordingly, the cavity may beinhibited or prevented from being formed between the first semiconductordevice 11 and the second semiconductor device 12. Accordingly, a yieldof the semiconductor package 1 may be improved.

The first and second via structures 1200 and 2200 may include first andsecond barrier patterns 1210 and 2210, first and second seed patterns1220 and 2220, and first and second conductive vias 1230 and 2230,respectively. The first and second pad structures 1300 and 2300 mayinclude first and second seed pads 1310 and 2310 and first and secondconductive pads 1320 and 2320, respectively.

As illustrated in FIG. 5A, a top surface of the second via structure2200 may be substantially coplanar with a top surface of the second padstructure 2300 and a top surface of the second insulating layer 2120. Athird connection terminal 3400 may be in direct contact with the secondvia structure 2200 and the second pad structure 2300. A third adhesivefilm 3500 may be disposed on the top surface of the second insulatinglayer 2120 to seal the third connection terminal 3400. A top surface ofthe third via structure 3200 may be substantially coplanar with a topsurface of the third pad structure 3300 and a top surface of the thirdinsulating layer 3120. A fourth connection terminal 4400 may be indirect contact with the third via structure 3200 and the third padstructure 3300. A fourth adhesive film 4500 may be disposed on the topsurface of the third insulating layer 3120 to seal the fourth connectionterminal 4400. Each of the third and fourth adhesive films 3500 and 4500may include at least one of the materials described as the examples ofthe second adhesive film 2500. The molding layer 5000 may be provided onthe package substrate 1000 to cover the first to fourth semiconductordevices 11, 12, 13, and 14.

According to some example embodiments of the inventive concepts, the topsurface of the via structure and the top surface of the pad structuremay be exposed at the top surface of the semiconductor device. Theconnection terminal may be in contact with the via structure and the padstructure. The top surface of the via structure may be substantiallycoplanar with the top surface of the pad structure and the top surfaceof the insulating layer. Thus, the adhesive film may be disposed on thetop surface of the insulating layer to seal the connection terminal.

The insulating layer may buffer or reduce the stress applied to the padstructure. The pad structure may be embedded in the insulating layer toimprove the adhesive strength between the pad structure and theinsulating layer. The angle between the bottom surface and the sidewallof the pad structure may be adjusted, and thus the stress may not beconcentrated in the edge or corner of the pad structure. Thus,reliability of the semiconductor device may be improved.

While the inventive concepts have been described with reference toexample embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirits and scopes of the disclosed example embodiments.Therefore, it should be understood that the above example embodimentsare not limiting, but illustrative. Thus, the scopes of the inventiveconcepts are to be determined by the broadest permissible interpretationof the following claims and their equivalents, and shall not berestricted or limited by the foregoing description.

What is claimed is:
 1. A method for manufacturing a semiconductordevice, the method comprising: forming a via structure penetrating asubstrate; forming an insulating layer on a first surface of thesubstrate; forming a trench in the insulating layer, an end portion ofthe via structure protruding from a bottom surface of the trench;forming a pad structure in the trench and on the insulating layer tocover the end portion of the via structure; and performing aplanarization process on the pad structure to expose the via structureand a top surface of the insulating layer, wherein an angle between abottom surface and a sidewall of the pad structure is in a range between90 degrees and 120 degrees.
 2. The method of claim 1, wherein a topsurface of the pad structure is disposed at a substantially same levelwith a top surface of the via structure and the top surface of theinsulating layer, after the performing a planarization process.
 3. Themethod of claim 1, further comprising: mounting a first uppersemiconductor device on the substrate, wherein the first uppersemiconductor device includes a first substrate and a first connectionterminal on a bottom surface of the first substrate, and wherein thefirst connection terminal is in contact with the pad structure and thevia structure after the mounting a first upper semiconductor device. 4.The method of claim 3, further comprising: mounting a second uppersemiconductor device on the first upper semiconductor device, whereinthe first upper semiconductor device further includes a first viastructure penetrating the substrate and a first pad structuresurrounding an upper sidewall of the first via structure, and wherein asecond connection terminal is in contact with the first pad structureand the first via structure after the mounting a second uppersemiconductor device.
 5. The method of claim 1, wherein the forming atrench comprises: patterning the insulating layer to form a preliminarytrench, the preliminary trench having a sidewall substantiallyperpendicular to a bottom surface thereof; and performing a thermalprocess on the insulating layer to form the trench, wherein the trenchhas a sidewall inclined to the bottom surface thereof.
 6. The method ofclaim 1, further comprising: forming transistors on a second surface ofthe substrate; forming insulating pattern on the second surface of thesubstrate to cover the transistors; and forming an interconnectionstructure in the insulating pattern, the interconnection structureelectrically connected to the via structure.
 7. A method formanufacturing a semiconductor device, the method comprising: forming avia structure penetrating a substrate; forming an insulating layer on afirst surface of the substrate; forming a trench in the insulating layerto expose an upper portion of the via structure; forming a conductivestructure in the trench and on the insulating layer to cover the upperportion of the via structure; and planarizing the conductive structureto expose the via structure and a top surface of the insulating layer,wherein an angle between a bottom surface and a sidewall of conductivestructure is an obtuse angle.
 8. The method of claim 7, wherein a topsurface of the via structure is disposed at a substantially same levelwith a top surface of the conductive structure and the top surface ofthe insulating layer, after the planarizing the conductive structure. 9.The method of claim 7, further comprising: mounting a first uppersemiconductor device on the substrate; and mounting a second uppersemiconductor device on the first upper semiconductor device, whereinthe first upper semiconductor device includes a first substrate, a firstconnection terminal on a bottom surface of the first substrate, a firstvia structure penetrating the substrate, and a first conductivestructure surrounding un upper sidewall of the first via structure,wherein the first connection terminal is in contact with the conductivestructure and the via structure after the mounting a first uppersemiconductor device, and wherein a second connection terminal is incontact with the first conductive structure and the first via structureafter the mounting a second upper semiconductor device.
 10. The methodof claim 7, wherein the forming a via structure comprises: forming a viahole in the substrate to penetrate a second surface of the substrate;forming a barrier pattern on a sidewall of the via hole; and forming aconductive via on the barrier pattern to fill the via hole, wherein atop surface of the barrier pattern and a top surface of the conductivevia are disposed at a substantially same level as the top surface of theinsulating layer, after the planarizing.
 11. The method of claim 10,wherein the forming a via structure further comprises: forming a seedpattern on the barrier pattern, wherein the seed pattern is disposedbetween the barrier pattern and the conductive via, wherein a topsurface of the seed pattern is disposed at a substantially same level asthe top surface of the insulating layer, after the planarizing.
 12. Themethod of claim 10, further comprising: forming a liner layer coveringthe sidewall of the via hole and provided between the substrate and thebarrier pattern; performing a thinning process on the first surface ofthe substrate such that the via structure protrudes from the thinnedsubstrate; and removing a portion of the liner layer to expose an endportion the via structure.
 13. The method of claim 7, wherein theforming a conductive structure comprises: forming a seed pad on thebottom surface, a sidewall of the trench, and a sidewall of an endportion of the via structure; and forming a conductive pad on the seedpad to fill the trench, wherein a top surface of the seed pad and a topsurface of the conductive pad are disposed at a substantially same levelwith the top surface of the insulating layer, after the planarizing. 14.The method of claim 7, wherein the via structure has a first width atthe first surface of the substrate and a second width at a secondsurface of the substrate, the first width is less than the second width,and the second surface of the substrate is opposite to the first surfaceof the substrate.
 15. A method for manufacturing a semiconductor device,the method comprising: forming a via hole in a substrate; forming abarrier pattern on a sidewall of the via hole; forming a conductive viaon the barrier pattern to fill the via hole; forming a circuit layer ona lower surface of the substrate; forming an insulating layer includingan organic material on an upper surface of the substrate; forming atrench in the insulating layer so that an upper portion of theconductive via protrudes from a bottom surface the trench; forming a padstructure in the trench to cover the upper portion of the conductivevia; and performing a planarization process on the pad structure toexpose the conductive via, the barrier pattern, and a top surface of theinsulating layer.
 16. The method of claim 15, wherein an angle betweenthe bottom surface and a sidewall of the trench is an obtuse angle. 17.The method of claim 15, wherein a top surface of the pad structure isdisposed at a substantially same level with a top surface of the barrierpattern, a top surface of the conductive via, and the top surface of theinsulating layer, after the performing the planarization process. 18.The method of claim 15, further comprising: providing a firstsemiconductor device including a first substrate, a first connectionterminal on a bottom surface of the first substrate, a first viastructure penetrating the substrate, and a first pad structuresurrounding un upper sidewall of the first via structure; mounting thefirst semiconductor device on the substrate so that the first connectionterminal is in contact with the pad structure and the conductive via;and mounting a second semiconductor device on the first semiconductordevice so that a second connection terminal of the second semiconductordevice is in contact with the first pad structure and the first viastructure.
 19. The method of claim 15, wherein forming the pad structurecomprises: forming a seed pad on the bottom surface, a sidewall of thetrench, and a sidewall of the upper portion of the conductive via; andforming a conductive pad on the seed pad to fill the trench.
 20. Themethod of claim 19, wherein an outer sidewall of the barrier pattern isin contact with the seed pad.